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uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
verilog_rs232
- 用verilog实现串行口UART控制器，适用于XILINX器件-verilog UART controller
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
uart
- 自己写的Verilog写的串口程序，实现收发功能。方法不错，可以参考下。-verilog...uart...
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
uart_verilog
- UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginn
uart16550
- Implementation of the UART 16550 model with verilog langugue
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
RS232
- It s combination logic for UART. Edited in verilog-HDL.
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
Verilog-UART
- UART With Verilog Unit for Transmission Unit for Reception
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
uartverilog
- 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
UART
- verilog 串口模块，高度集成，下载下就能用-verilog uart communication,easy use
UART
- xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
uart
- 用verilog编写的uart代码，比较适合初学者练练手，包含初始化，收发等模块-Written code with verilog uart, more suitable for beginners practice your hand, including initialization, sending and receiving modules
Verilog-uart
- Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
verilog-UART-Controler
- 使用verilog语言实现的UART控制器，包含发送和接收部分，波特率可调。-Using the UART controller verilog language, including sending and receiving part, the baud rate is adjustable.